Shareware Super Platinum 8

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Text File | 1994-01-19 | 73.8 KB | 1,957 lines

Cirrus Logic CL-GD 500/600 CL-GD 510/520 Flat Panel/LCD CL-GD 610/620 Flat Panel/LCD CL-GD 5320 The 64xx Flat Panel family: CL-GD 5410 CL-GD 6410 Flat Panel LCD 256k no banks. CL-GD 6420 Flat Panel/LCD 512k/1M? CL-GD 6412 CL-GD 6416 CL-GD 6440 CL-GD 6450 The 54xx Super VGA family: CL-GD 5401 AVGA 1. No banks CL-GD 5402 AVGA 2. Note: the 5401 and 5402 are sometimes sold as the Acumos AVGA1 and 2. CL-GD 6205 CL-GD 6215 CL-GD 6225 CL-GD 5420 CL-GD 5422 1024x768x256. CL-GD 5424 CL-GD 5426 Up to 2MB. Accelerated version of 5422. BitBLT CL-GD 5428 Newer version of 5426 CL-GD 5434 Next generation 64bit chip The 54xx series has a built in RAMDAC. 8 bit for the 5401/5402, 15/16bit for the 5420 and 15/16/24 bit for the 5422 and up. Other Chips: CL-GD 6340 LCD Panel Driver The 5xx/6xx Flat Panel family: This family strongly resembles the early Video 7 chips. Apparently Cirrus supplied at least one of the early Video 7 chips (Video7 OEM). 3C4h index 6 (W): bit 0-7 Writing ("Eagle ID" rol 4) will disable extensions. Writing "Eagle ID" will enable. Reading will return 0 if extensions are disabled, 1 if enabled The "Eagle ID" is read from 3d4h index 1Fh 3C4h index 80h (R/W): Miscellaneous Control 1 3C4h index 81h (R/W): Graphics Position 1 3C4h index 82h (R/W): Graphics Position 2 3C4h index 83h (R/W): Attribute Controller Index 3C4h index 84h (R/W): Write Control 3C4h index 85h (R/W): Timing Control 3C4h index 86h (R/W): Bandwidth Control 3C4h index 87h (R/W): Miscellaneous Control 2 3C4h index 88h (R/W): Horizontal Sync skew 3C4h index 89h (R/W): CGA, HGC Font Control 3C4h index 8Ah (R/W): Reserved 3C4h index 8Bh (R/W): Screen B preset row scan 3C4h index 8Ch (R/W): Screen B start address high 3C4h index 8Dh (R/W): Screen B start address low 3C4h index 8Eh (R): Version Code 3C4h index 8Fh (R): Version Code 3C4h index 90h (R/W): Vertical Retrace Start 3C4h index 91h (R/W): Vertical Retrace End 3C4h index 92h (R/W): Lightpen High 3C4h index 93h (R/W): Lightpen Low 3C4h index 94h (R/W): Pointer Pattern Address High 3C4h index 95h (R/W): Cursor Height Adjust 3C4h index 96h (R/W): Caret Width 3C4h index 97h (R/W): Caret Height 3C4h index 98h (R/W): Caret Horizontal Position High 3C4h index 99h (R/W): Caret Horizontal Position Low 3C4h index 9Ah (R/W): Caret Vertical Position High 3C4h index 9Bh (R/W): Caret Vertical Position Low 3C4h index 9Ch (R/W): Pointer Horizontal Position High 3C4h index 9Dh (R/W): Pointer Horizontal Position Low 3C4h index 9Eh (R/W): Pointer Vertical Position High 3C4h index 9Fh (R/W): Pointer Vertical Position Low 3C4h index A0h (R/W): Graphics Controller Memory Latch 0 3C4h index A1h (R/W): Graphics Controller Memory Latch 1 3C4h index A2h (R/W): Graphics Controller Memory Latch 2 3C4h index A3h (R/W): Graphics Controller Memory Latch 3 3C4h index A4h (R/W): Clock Select 3C4h index A5h (R/W): Cursor (Caret and pointer) Attribute 3C4h index A6h (R/W): Internal Switch Source 3C4h index A7h (R/W): Status Switch Control 3C4h index A8h (R/W): NMI Mask 1 3C4h index A9h (R/W): NMI Mask 2 3C4h index AAh (R/W): Reserved 3C4h index ABh (R): NMI Status 1 3C4h index ACh (R): NMI Status 2 3C4h index ADh (R/W): 256 Color mode Page Control 3C4h index AEh (R): NMI data cache (Four 24 bit words) 3C4h index AFh (R/W): Active Adapter State 3C4h index B0h..BFh (R/W): Scratch Registers 3C4h index C0h..FFh (R/W): Reserved 3d4h index Ch (R/W): Screen A start address Hi Must be cleared before the Eagle ID Register (3d4h index 1Fh) can be read. 3d4h index 1Fh (R): Eagle ID register bit 0-7 Eagle ID. Used for test of 3C4h index 6. Reading this register will return the content of 3d4h index 0Ch XORed with the Eagle ID value. ECh for CL-GD 510/520, CAh for 610/620. EAh for Video7 boards. Memory locations: $C000:$6 2 bytes 'CL' if Cirrus Bios Modes for the CL-GD510/520: 40h T 100 30 41h T 100 50 42h T 100 60 50h T 132 30 51h T 132 50 52h T 132 60 53h T 80 60 62h G 640 450 16 63h G 720 540 16 64h G 800 600 16 Other sources claim: 15h T 132 25 2 (8x14) 16h T 132 44 2 (8x8) 18h T 132 30 2 (8x) 1Eh T 132 25 16 (8x8) 1Fh T 132 25 16 (8x14) 20h T 132 44 16 (8x8) 22h T 132 30 16 (8x) 31h T 100 37 2 40h G 720 540 16 PL4 50h G 640 400 256 packed 51h G 512 480 256 packed Note: not supported in all Bios'es 63h G 720 540 16 PL4 64h G 800 600 16 PL4 6Ah G 800 600 16 PL4 Mode 50h and 51h use a special system where four pixels are stored at the same byte address in plane 0,1,2 and 3 respectively. GD5410, 64xx series: 3CEh index 0Ah (R/W): Enable Extension bit 0-7 Write ECh to enable extensions, CEh to disable. Reads as 1 if enabled, 0 if not. 3CEh index 0Bh (R/W): Attribute Controller Index (ARX) r/w with toggle bit 0-4 Attribute Register Index 5 Enable Video 7 Toggle ARX to Data 3CEh index 0Ch (R/W): CR11 bit 7 at Extension bit 7 Write Protect 3d4h index 0-7. 3CEh index 0Dh (R/W): CPU Base Address Control (not 6410) bit 0 Enable Page Remapping 1 Enable 64K Remapping page size if set, 32K if clear 2 If set use 3CEh index 0Eh for reads and index 0Fh for writes. if clear both reads and writes use index 0Eh. 4 (6440) Enable Linear Addressing 7 (not 6440) Enable I/O Ext Addr Remapping 3CEh index 0Eh (R/W): CPU Base Address Mapping Register A (not 6410) bit 0-7 Bank number in 4K units. If 3CEh index 0Dh bit 2 is set this register is only used for reads, if clear this register is used for both reads and writes. 3CEh index 0Fh (R/W): CPU Base Address Mapping Register B (not 6410) bit 0-7 Bank number in 4K units. If 3CEh index 0Dh bit 2 is set this register is used for writes. 3CEh index 34h (R/W): Cursor Location Extension (5410 only) bit 0-3 Cursor Location Address bit 16-19 3CEh index 60h (R/W): Horizontal Total Extension bit 0-7 Bit 8 is in 3CEh index 64h bit 5. 3CEh index 61h (R/W): Horizontal Blank Start Extension bit 0-7 Bit 8 is in 3CEh index 62h bit 7. 3CEh index 62h (R/W): Horizontal Blank End Extension bit 0-4 Horizontal Blank End Extension 7 Horizontal Blank Start Extension bit 8. Bits 0-7 are in index 61h. 3CEh index 63h (R/W): Horizontal Retrace Start Extension bit 0-7 Bit 8 is in 3CEh index 64h bit 6. 3CEh index 64h (R/W): Horizontal Retrace End Extension bit 0-4 Horizontal Retrace End Extension 5 Horizontal Total Extension bit 8. Bits 0-7 are in index 60h. 6 Horizontal Retrace Start Extension bit 8. Bits 0-7 are in index 63h. 7 Horizontal Blank End bit 8. Bits 0-7 are in index 62h. 3CEh index 70h (R/W): Vertical Total Extension bit 0-7 Bits 8-10 are in index 78h and 79h 3CEh index 71h (R/W): Vertical Display Enable Extension bit 0-7 Bits 8-10 are in index 78h and 79h 3CEh index 72h (R/W): Vertical Blank Start Extension bit 0-7 Bits 8-10 are in index 78h and 79h. 3CEh index 73h (R/W): Vertical Blank End Extensions bit 0-7 Bit 8 is in index 78h 3CEh index 74h (R/W): Vertical Retrace Start Extension bit 0-7 Bits 8-10 are in index 78h and 79h. 3CEh index 75h (R/W): Vertical Retrace End Extension bit 0-3 3CEh index 78h (R/W): CR07 Extension bit 0 Vertical Total bit 8. Bits 0-7 are in index 70h 1 Vertical Display Enable bit 8. Bits 0-7 are in index 71h 2 Vertical Retrace Start bit 8. Bits 0-7 are in index 74h 3 Vertical Blank Start bit 8. Bits 0-7 are in index 72h 4 Line Compare bit 8. 5 Vertical Total bit 9 6 Vertical Display Enable bit 9. 7 Vertical Retrace Start bit 9 3CEh index 79h (R/W): Vertical Overflow beyond CR07 bit 0 Vertical Total bit 10 1 Vertical Display Enable bit 10 2-3 Vertical Blank Start bit 9-10. 4 Vertical Retrace Start bit 10 3CEh index 7Ah (R/W): Coarse Vertical Retrace Skew for Interlaced bit 0-7 Coarse Vertical Retrace Skew for Interlaced Odd Fields in Character Clock Periods. 3CEh index 7Bh (R/W): Fine Vertical Retrace Skew bit 0-1 Fine Vertical Retrace Skew for Interlaced Odd Fields in Dot Clock Periods 3CEh index 7Ch (R/W): Start Address Extension bit 0-3 Screen A Start Address Extension bits 16-19 3CEh index 80h (R/W): H/V Retrace Polarity Control (not 5410) bit 1 (6440) Interlaced Mode Enable 2 (6440) Double Character Clock for Horizontal Parameters 4 Enable Expanded Graphics 5 H/V Polarity Source Control 6 Horizontal Retrace Polarity 7 Vertical Retrace Polarity 3CEh index 81h (R/W): Display Mode (not 6440) bit 0 (not 5410) Select LCD Display if set, CRT if clear 2 (6420,5410) Interlaced Mode Enable 3 (not 5410) Enable CL-GD6340 Mode 4 (not 5410) Select Single Scan Panel 5 (not 5410) Enable AutoMAP 7 (not 5410) Enable Simulscan 3CEh index 82h (R/W): Character Clock bit 0-2 Character Clock Width. 1: 8pixels, 2:4pixels 3 Disable SR1[0] functionality ?? 5-6 (5410) 0: 2 CRT-clkin, 1: 1, 2: 4 7 (6440) Enable Internal Divided by 2 (for Pixel Doubling) 3CEh index 83h (R/W): Write Control bit 0 CRTC Vertical Parameters Write Protect 3d4h index 6, 7 (bit 0,2,3,5,7), 9 bit 5, 10h, 11h bit 0-3, 15h, 16h 1 (6440) Horizontal Parameters Write Protect (not 6440) CRTC Display Timing Effect Write Protect 3d4h index 7 (bit 1,6), 9, 0Ah, 0Bh, 12h, 14h 2 (not 6440) CRTC Vertical Display End Effect Protect 3d4h index 12h, 7 (bits 1,6) 3 (not 6440) CRTC Blank Effect Protect 3d4h index 2, 3 bits 0-3, 5 bit 7, 7 bit 3, 9 bit 5, 15h, 16h 4 (not 6440) CRTC Total/Retrace Effect Protect 6 (not 6440) Attribute Registers Write Protect (3C0h index 0-0Fh). 3CEh index 84h (R/W): Clock Select (not 6440) bit 1 (not 5410) Clock In Divide by 2 if set. 2-5 Clock Select 7 Select bit 2-3 as clock bit 0-1 rather than 3C2h bit 2-3. 3CEh index 85h (R/W): Virtual Switch Source (5410 only) 0-3 VGA Internal Switches for Analog Monitor 4 Enable Virtual Switches 3CEh index 86h (R/W): CRTC Test bit 1-3 (5410) CRTC Test Bits 4 CRTC Outputs Three-State Control 5 (6412,40) HSYNC, VSYNC Disable if set 3CEh index 87h (R/W): CRTC Spare Extension (Rev B only) bit 1 (6412) PVSYNC Configuration Pin 82: bit 4: bit 1: index 8Fh bit 4: LFS 0 0 0 FPVDE 0 0 1 VDE* 1 0 x PVSYNC 0 1 x 3 (6412) Enable Short VSYNC Total 4 (NOT 5410) VDE*/LFS Configuration on pin 99. If set pin 99 is VDE*, if clear pin 99 is LFS 6 (6412) Enable short HTOT (HDE+7) 7 (6412) Enable short VTOT (VDE+4) (6410,20) Invert VDE* Polarity on pin 99 6-7 (5410) Interlace Test 0-1 3CEh index 8Fh (R/W): CRTC BIOS Configuration (not 6440) bit 0-1 Clock Select Pin-out Configuration 2 (6412) If set SUSPEND* input, if clear FRA8 input 3 (6412) If set VDCLK I/O output, if clear FPVDCLK 4 (6412) If set FPVDE output, if clear LFS output 5 (6412) SUSPEND* pin Configuration. SUSPEND* if set, FRA8 if clear 6 (6412) Frame Accelerator Control bit. Set if the system power down the Frame Accelerator DRAM 7 (6412,20) Enable Retrace Line Clocks 3CEh index 90h (R/W): VMC Control bit 0 Scan Line Double Control 1 RAS* Precharge. Extended if clear, normal if set 2 (5410) DMC2 3 Display Memory Refresh Control Extension 5-6 (5410) DMC5-6 6 (6410 rev B,6420) Power Sequencing Status Bit. Note: The undefined bits should be set to 0 when writing this register. 3CEh index 91h (R/W): CRT Circular Buffer Policy Selection bit 6-7 (R) Reserved Note: The undefined bits should be set to 0 when writing this register. 3CEh index 92h (R/W): Font Control bit 0-1 Font Control Address Extension 3 (6410,20) Enable Software Expanded Text 5 (not 5410) Enable Full Height Cursor 6 (not 5410) Text Expansion Method Select 7 (not 5410) Enable Hardware Expanded Text 3CEh index 93h (R/W): Full Frame-Accelerator Bottom Half Start (6440) bit 0-7 Bottom Half Start Address 3CEh index 93h (R/W): CPU Interface Test Register (5410) bit 6-7 CTR6-7 3CEh index 94h (R/W): Full Frame-Accelerator Misc. Control 1 (6440) bit 0 Frame Accelerator Selection. Full if set, Half if clear Note: The undefined bits should be set to 0 when writing this register. 3CEh index 95h (R/W): CRTC Circular Buffer Delta and Burst bit 0-3 Delta number 4-7 Burst number 3CEh index 96h (R/W): Display Memory Control Test Register bit 0 Latch Monitor ID 1 (6420) Frame Accelerator Three-State control (6440,5410) Video Memory Data M1D, M3D Three-State Control 2 Video Memory Data M0D, M2D Three-State control 3 Video Memory & Address Three-State control 4 (5410) Disable Fast-Page Mode Note: The undefined bits should be set to 0 when writing this register. 3CEh index 97h (R/W): Monitor Switches Read Back bit 0 (6440) 14MHz Clock Source 3-7 (6440) Reserved for BIOS 4-7 (not 6440,5410) Panel Type Switches 7 (5410) Interlace 3CEh index 98h (R/W): Scratch bit 0-7 3CEh index 99h (R/W): Pull Up/Down Configuration bit 0 BIOS address. C000h if clear, E000h if set 1 (5410) CPU Bus Type. 0: ISA, 1: MCA 1-2 (6440) CPU Bus Type. 0: Local Bus, 1: PI bus, 2: ISA bus 2 (not 6440) Disable VGA address space 3 Sleep at 46E8h if set, 3C3h if clear 4 BIOS is 16bit if set, 8bit if clear 5 (6440) VGA Address space 6 (6440) Disable ST100 Effect 7 (6440) CPU clock select/ISA I/O select 3CEh index 9Ah (R/W): Video Memory Configuration bit 0-7 (not 6440,5410) Reserved. should be programmed to 0. 0-2 (6440) Memory Width 6-7 (5410) RAMDAC Select 0-1 3CEh index 9Bh (R/W): Miscellaneous Pin Configuration bit 0 Enable Sequencer Clock (SQCLK) inversion 1 On Chip Monitor Sense Enable if set, disable if clear 3-4 (not 6440,5410) INTERNAL/MOD Pin Configuration. 0: INTERNAL, 1: MODULATION 5-6 (not 6440,5410) LLCLK/DE Configuration. 0: LLCLK, 1: DE (for GD6340), 3: Pins 98/99=PHSYNC/PVSYNC 7 (6412) Paged BIOS Disable. If set pins 62-64 are TIMER*, PO1 and SSCLK if clear pins 62-64 are BIOS address bit 13-15 Note: The undefined bits should be set to 0 when writing this register. 3CEh index 9Ch (R/W): PS/2 Monitor ID Read-back bit 5-7 Monitor ID. 2: 8514, 5: 8503, 6: 8512/8513, 7: no monitor 3CEh index 9Dh (R/W): Miscellaneous Configuration 2 (6412 only) bit 0 FPVDCLK Delay. If set delay FPVDCLK by 1/2 Video Clock (VDCLK) 1 Select OE* Delay. If set OE* is delayed by one Memory Clock (SQCLK) 6 5v/3v Monitor Sense Select. 5V if set, 3.3V if clear 7 Select OSC as SQCLK. If set SQCLK is derived from OSC, if clear from an input 3CEh index 9Dh (R/W): Configuration 1 Register (5410 only) bit 0-1 Bus Type 6 Use External SQCLK Synthesizer 7 Use External VDCLK Synthesizer 3CEh index 9Eh (R/W): Frame-Accelerator Even Frame Start Addr (6440) bit 0-7 Frame-Accelerator Even Frame Start Address 3CEh index 9Eh (R/W): Display Memory Configuration High (5410) bit 0-2 SQCLK Frequency 3-4 DRAM Width 5-7 DRAM Depth 3CEh index 9Fh (R/W): Frame-Accelerator Odd Frame Start Addr (6440) bit 0-7 Frame-Accelerator Odd Frame Start Address 3CEh index 9Fh (R/W): Display Memory Configuration Low (5410) bit 0 DMCR0 1-3 Display Memory Bus Width 4-6 Display Memory Bus Depth 3CEh index A0h (R/W): Bus Interface Unit Control bit 0 Disable BIOS ROM 1 Disable Sleep Mechanism 2 (not 5410) Enable Write Protect RAMDAC 3 MEMCS16* Mode Select 4 Enable 16bit Memory 5 (6440) Enable 16bit I/O 6 (5410) Enable 16bit I/O (not 5410) Disable CPU Address Scramble 7 (5410) Enable 16bit Interface in Planar Modes 3CEh index A1h (R/W): Three-State & Test Control bit 3 All other Output & I/O pins Three-State Control 5 If set the CRTC Offset (3d4h index 13h) and Display Start Address (3d4h index 0Ch,0Dh).are multiplied with 4. Set in extended 256color modes. 7 (not 5410) Disable I/O Read Note: The undefined bits should be set to 0 when writing this register. 3CEh index A2h (R/W): BIOS Page Selection (not 5410) bit 0-2 Select ROM BIOS Page 3CEh index A6h (R/W): Wait State Controls bit 0 Disable Memory Write Wait State Control 1 Disable I/O Read Wait State 2 Enable 0 Wait State for Memory Write 3 (not 6440) Disable RAMDAC I/O Wait State 4 Disable I/O Write Wait State 6 (not 5410) BIOS Wait-State Control. 0 Wait States if set 7 (R) Bus width Status Bit. 16bit if set, 8bit if clear 3CEh index A7h (R/W): General Programmable I/O Port Control (not 5410) bit 0 (6440) Output pin PO0 Control 1 Output pin PO1 control 2 (6410,20,40) Output pin PO2 Control 3 (6440) Output pin PO3 Control 4 (6440) Write Protect 3CEh index 0Dh 6 (6440) Enable PO[3:0] 3CEh index A9h (R/W): Bus Interface Unit Cache Control bit 0 (5410) Enable Read from Write FIFO 1 Enable Cache Read 2 (6440,5410) Enable Write Plane-Select Compaction in Write Mode 0 3 (6410,12,5410) Enable Write-Overwrite Compaction in modes 2,3 4 (5410) Enable 16bit Peripheral in Planar Modes 5-6 Internal BIU Timing to control delays 3CEh index AAh (R/W): Design Revision bit 0-3 Design Revision 4-7 Design ID (Major version): 4: CL-GD6440 5: CL-GD6412 6: CL-GD5410 7: CL-GD6420 8: CL-GD6410 3CEh index ABh (R/W): Mask Revision (not 5410) bit 0-7 3CEh index AEh (R/W): Alternate Extension Decode High (5410,6412 only) bit 0-7 Bits 8-15 of the value. Bits 0-7 are in index AFh 3CEh index AEh (R/W): Color Expansion Pixel Mask (6440 only) bit 0-7 3CEh index AFh (R/W): Alternate Extension Decode Low (5410,6412 only) bit 0-7 Bits 0-7 of the value. Bits 8-15 are in index AEh 3CEh index B0h (R/W): Color Expansion Control (6440 only) bit 0 Enable Color Expansion 1 Enable by 8 Address Mode 2 Write Mode 4/5 Control 4 Enable Enhanced Writes for 16bit pixels 3CEh index B1h (R/W): Linear Address Map (6440 only) bit 0-3 Linear Address Map 3CEh index B2h W(R/W): Foreground Color for Color Expansion (6440 only) bit 0-15 Foreground color for color expansion 3CEh index B4h W(R/W): Background Color for Color Expansion (6440 only) bit 0-15 3CEh index BAh (R/W): Scratch Pad 0 bit 0-7 3CEh index BBh (R/W): Scratch Pad 1 bit 6-7 Video Memory: 0: 256K, 1: 512K, 2: 768K, 3: 1024K 3CEh index BCh (R/W): Scratch Pad 2 bit 0-7 3CEh index BDh (R/W): Scratch Pad 3 bit 0-7 3CEh index BEh (R/W): Scratch Pad 4 bit 0-7 3CEh index BFh (R/W): Scratch Pad 5 bit 0-7 3CEh index C0h (R/W): Attribute and Graphics Control bit 0 (not 5410) Enable Foreground Enhancement 1 Bypass Internal Palette 2 (6412) Enable 4bit Single-Scan Monochrome Panel Support (6440) Attribute Emulation (5410) Disable 3C0h index 14h 3 Enable Background Color Enhancement 3CEh index C1h (R/W): Cursor Attributes bit 0 Enable Cursor Blinking 1-2 Cursor Blinking Rate 3 Cursor Mode. Invert if set, replace if clear 4 Invert Border Color 5 (not 5410) Cursor Color Control 3CEh index C2h (R/W): Graphics Controller Memory Latch 0 bit 0-7 3CEh index C3h (R/W): Graphics Controller Memory Latch 1 bit 0-7 3CEh index C4h (R/W): Graphics Controller Memory Latch 2 bit 0-7 3CEh index C5h (R/W): Graphics Controller Memory Latch 3 bit 0-7 3CEh index C8h (R/W): DAC Power Control bit 1 (6410,12,40) Select 16color Extended mode (Packed-pixel) 2 (6440) Enable 256 Color Modes 5 Enable Force Blank to RAMDAC 6 (6440) Grey Scale Data from Attribute Note: The undefined bits should be set to 0 when writing this register. 3CEh index C9h (R/W): Graphics and Attribute Test bit 0-2 (5410) GAT bits 0-2 3 (6410,12,40,5410) Enable 9dot Font 4 (not 6440) Three-State Pixel data & VDCLK 5 (6440) LSB value of Red and Blue and Green (5410) Red/Blue LSB 6 (6440) Select 16bit/pixel green map (5410) Green LSB 7 (6440,5410) Enable True Color 3CEh index D0h (R/W): Flat Panel Column Offset (not 6440) bit 0-7 Bit 8 is in index D4 bit 0. 3CEh index D1h (R/W): Flat Panel Horizontal Displayed (not 6440) bit 0-7 Bit 8 is in 3CEh index D4h bit 1 3CEh index D2h (R/W): Flat Panel Row Offset (not 6440) bit 0-7 Bits 8-9 are in 3CEh index D4 bits 2-3 3CEh index D3h (R/W): Flat Panel Vertical Size (not 6440) bit 0-7 Bits 8-10 are in 3CEh index D4h bit 4-6 3CEh index D4h (R/W): Flat Panel Overflow (not 6440) bit 0 Column Offset bit 8. Bits 0-7 are in index 60h 1 Panel Horizontal Displayed bit 8. Bits 0-7 are in index D1h 2-3 Row Offset Overflow bits 8-9. Bits 0-7 are in index D2h 4-6 Panel Vertical Size Overflow bits 8-10. Bits 0-7 are in index D3h. 3CEh index D5h (R/W): Flat Panel Attribute LCD Control (not 6440) bit 0-1 9 Dots Text Reduction 2 (R) Stand-by Mode Status bit 3 Enable Attribute Emulation 4 Enable Extra Line Clk 5 Enable Reverse Video in Graphics Mode 6 Enable Reverse Video in Text Mode 7 Enable AutoMAP 3CEh index D6h (R/W): Flat Panel Grey Scale Offset (not 6440) bit 0 Select Grey Scale offset 4 (default=13) 1 Power Sequencing Control 2 Power Sequencing Time Control 4 (6420 & 6410 rev B) Enable 8bit Plasma Interface 5 (6420 & 6410 rev B) Enable Intermodulation 6 Enable Horizontal Stipling 7 Enable Vertical Stipling 3CEh index D7h (R/W): Flat Panel Retrace LLCLK Control (not 6440) bit 0-4 Retrace LLCLK counter 3CEh index D8h (R/W): Flat Panel Frame Color (not 6440) bit 0-3 Frame Color 4 Enable Frame Color 6 (6410 rev B,12,20) Enable EPSON FPLCLK 3CEh index D9h (R/W): Flat Panel AC Modulation (not 6440) bit 0-7 3CEh index DAh (R/W): Flat Panel Display Control (not 6440) bit 0 (6420, 6410 rev B) Force 32 Grey Shades 1-2 Panel Vertical Alignment Control 3-4 Panel Size Selection 5-7 RGB Weight Control 3CEh index DBh (R/W): Standby Timer Control (not 6440) bit 0-5 Standby Mode Time Interval in minutes 6-7 Standby Mode. 0: disable, 1: screen save, 2: video memory 3CEh index DCh (R/W): Flat Panel Color Configuration (not 6440) bit 0 9bit Color Panel Select 1 MOD/FPHDE/P8 pin function control. If set P8 is output, if clear MOD is output if bit 0 is clear, FPHDE if set 3CEh index E0h (R/W): Flat Panel Column Offset (6440 only) bit 0-7 3CEh index E1h (R/W): Flat Panel Horizontal Displayed Size (6440 only) bit 0-7 Bit 8 is in index E4h bit 1. 3CEh index E2h (R/W): Flat Panel Row Offset (6440 only) bit 0-7 Bits 8-9 are in index E4h bit 2-3 3CEh index E3h (R/W): Flat Panel Vertical Size (6440 only) bit 0-7 Bits 8-10 are in index E4h bit 4-6 3CEh index E4h (R/W): Flat Panel Overflow (6440 only) bit 0 Column Offset bit 8. Bits 0-7 are in index E0h 1 Panel Horizontal Displayed bit 8. Bits 0-7 are in index E1h 2-3 Row Offset Overflow bits 8-9. Bits 0-7 are in index E2h 4-6 Panel Vertical Size Overflow bits 8-10. Bits 0-7 are in index E3h 3CEh index E5h (R/W): Flat Panel Horizontal Centering Offset (6440 only) bit 0-7 Bit 8 is in index E7h bit 0 3CEh index E6h (R/W): Flat Panel Horizontal Centering Offset-9Dot (6440 only) bit 0-7 Bit 8 is in index E7h bit 1 3CEh index E7h (R/W): Flat Panel Horizontal Centering Overflow (6440 only) bit 0 Flat Panel Horizontal Centering bit 8. Bits 0-7 are in index E5h 1 Flat Panel Horizontal Centering (9Dot) bit 8. Bits 0-7 are in index E6h 2 Flat Panel Horizontal Size Adjust 3CEh index E8h (R/W): Flat Panel Pin Configuration (6440 only) bit 0 Standby/Suspend Pin Status. If set Standby Timer Status is output on pin 152, if clear Suspend Mode Status is output on pin 152. 1 Enable FPHDE Control 2 Flat Panel Drive. If set 100%, if clear 60% 3 GD6440 Core at 3 Volts. If set 5V, if clear 3.3V 3CEh index E9h (R/W): Flat Panel Type Control (6440 only) bit 0-2 Flat Panel Size Selection. 0: 640x480, 1: 640x400, 2: 1280x1024/1280x960 3 Flat Panel Scan Type 5-6 Extra Line Clock Enable. 0,1: None, 2: 1 extra, 3: 2 extra line clocks 3CEh index EAh (R/W): Flat Panel Power Control (6440 only) bit 0 Power Sequence Status 1 Standby on Status 2 Sequencer Flat Panel Power 3-5 Standby Mode Selection 6 Enable External Suspend Pin 3CEh index EBh (R/W): Flat Panel Standby Timer (6440 only) bit 0-7 3CEh index ECh (R/W): Flat Panel Misc 1 Control (6440 only) bit 0-1 Vertical Alignment Control. 0: Top, 1: Bottom, 2,3:Center 2 Enable Horizontal Centering 3 Grayscale Offset Value 4-5 Display Type Select. 0: CRT, 1: Flat Panel, 2,3: SimulSCAN 6 Grayscale Offset Pattern Select 7 Invert FPVDE 3CEh index EDh (R/W): Flat Panel Retrace FPCLK (6440 only) bit 0-4 Programmed Burst of Line Clocks 5-6 Retrace Line Clock Control 7 Fast Line Clock 3CEh index EEh (R/W): Flat Panel Test Control (6440 only) bit 0-7 Reserved 3CEh index F0h (R/W): Flat Panel Clock Control (6440 only) bit 0-3 FPVDCLK Control 4-5 FPVDCLK Enable Control 6 Invert FPVDCLK 7 Invert FPHDE 3CEh index F1h (R/W): Flat Panel Data Control (6440 only) bit 0-4 Flat Panel Video Data Output Format Control 5 FPHSYNC/FPVSYNC Polarity Source Control 6 FPHSYNC Polarity Control 7 FPVSYNC Polarity Control 3CEh index F2h (R/W): Flat Panel AC Modulation (6440 only) bit 0-7 3CEh index F3h (R/W): Flat Panel FPHSYNC Skew (6440 only) bit 0-6 FPHSYNC Skew 3CEh index F4h (R/W): Flat Panel FPVSYNC Skew (6440 only) bit 0-4 FPVSYNC Skew 5 FPVSYNC Width 6-7 FPHSYNC Width 3CEh index F5h (R/W): Memory Clock Select Factor (6440 only) bit 0-4 Memory Clock Numerator "N" 5-7 Memory Clock Denominator "D" 3CEh index F6h (R/W): CRT Clock Select "N" Factor (6440 only) bit 0-6 CRT Clock Numerator "N" 7 Clock Source Control 3CEh index F7h (R/W): CRT Clock Select "D" Factor (6440 only) bit 0-3 CRT Clock Denominator "D" 4-5 CRT Clock Divide 6 Memory Clock Invert 7 CRT Clock Invert 3CEh index F8h (R/W): Flat Panel Mapping RAM Pointer (6440 only) bit 0-5 Pointer to the Mapping RAM for I/O Read/Write 7 Enable I/O Access of Mapping RAM 3CEh index F9h (R/W): Flat Panel Mapping RAM Data (6440 only) bit 0-7 Mapping RAM Data 3CEh index FAh (R/W): Flat Panel Stippling Control (6440 only) bit 0 Enable 32 Shades in All Stippling Cases 1-2 Stippling Select 3-5 Stippling Bit Select 6 Enable Inter-modulation 3CEh index FBh (R/W): Flat Panel Color Control (6440 only) bit 0 Blue Color Weighting 1 Green Color Weighting 2-3 Red Color Weighting 4 Green Data from LUT 5 Enable Reverse Video in Graphics Modes 6 Enable Reverse Video in Text Mode 3CEh index FCh (R/W): Flat Panel Frame Color 1 (6440 only) bit 0-3 Frame Color Bits for Red 4 Enable Frame Color 3CEh index FDh (R/W): Flat Panel Frame Color 2 (6440 only) bit 0-3 Frame Color Bits for Blue 4-7 Frame Color Bits for Green Video Modes: 002Dh G 640 400 256 P8 002Eh G 640 480 256 P8 002Fh G 648 480 256 P8 ;Weird resolution 0030h G 800 600 256 P8 0037h G 1024 768 16 PL4 0041h T 100 50 16 TXT 0042h T 100 60 16 TXT 0044h T 100 25 16 TXT 0051h T 132 50 16 TXT 0052h T 132 60 16 TXT 0053h T 80 60 16 TXT 0054h T 132 25 16 TXT 0064h G 800 600 16 PL4 006Ah G 800 600 16 PL4 GD62xx series: The 62xx series is very similar to the early 54xx. The 62xx series can display simultaneously on CRT and LCD. There are two extra register banks (CX and RX) at 3d4h. How to select ? 3C4h index 2 (R/W): Map Mask bit 0-7 Enable writing pixel bits 0-7 ????? Note: See the VGA section for the normal use of this register 3C4h index 6 (R/W): Unlock ALL Extensions bit 0-2,4 Writing 12h to this register enables extensions. Read back 0Fh if locked. Bits 3,5-7 are ignored on write. 3C4h index 7 (R/W): Extended Sequencer Mode bit 0 Enable High-Resolution 256 Color modes if set 4-6 (R) Configuration switch 0-2 (MD[14:12]) 3C4h index 8 (R/W): Miscellaneous Control bit 0-2 Switch 1-3 Readback (Panel type, Monitor type, Local bus config). 3 Select active polarity of input SUSPEND for suspend mode. .If set low is true, if clear high is true (default at reset). 4 Enable IO(60h) read detect to reset backlight timer 5 Enable IO(60h) read detect to reset standby timer 6 Disable MSC16* for Display Memory 7 Select symmetrical DRAM addressing for paged-mode on CRT Set when using DRAM 9-bit addressing at 132 col CRT 3C4h index 9 (R/W): Scratch Register 0 bit 0 Set to center 2-4 Monitor type. 0: 31,5kHz Std VGA. IBM 8512,8503 1: 31.5, 35.5 kHz IBM 8514 2: 31.5, 35.1 kHz NEC 2A 3: 31.5 - 35.5 kHz NEC II 4: 31.5 - 38 kHz Multi Freq. NEC 3D 5: 31.5 - 48 kHz Sony CPD-1304, NEC 3FG, Nanao 9065S, 9070U 6: 31.5 - 56.5 kHz NEC 4D,4FG, Nanao T240i 7: 31.5 - 64 kHz NEC 5D,5FG/6FG, Nanao T560i,T660i 7 Panel frequency 3C4h index 0Ah (R/W): Scratch Register 1 bit 0 Display mode 1 Disable expand 2 Enable 16bit mode. 4 Attribute emulation 5 Disable bold font 6 High refresh 7 Voltage 3C4h index 0Bh (R/W): VCLK 0 Numerator Register bit 0-6 VCLK 0 Numerator bits 0-6 3C4h index 0Ch (R/W): VCLK 1 Numerator Register bit 0-6 VCLK 1 Numerator bits 0-6 3C4h index 0Dh (R/W): VCLK 2 Numerator Register bit 0-6 VCLK 2 Numerator bits 0-6 3C4h index 0Eh (R/W): VCLK 3 Numerator Register bit 0-6 VCLK 3 Numerator bits 0-6 3C4h index 0Fh (R/W): DRAM Control bit 0-1 MCLK Select: 0: 50.1 MHz, 1: 44.7 MHz, 2: 25.0 MHz, 3: 37.5 MHz Select 25MHz if VCLK is <= 18MHz 2 RAS* Timing. 0: Extended (PD on MD[27], RAS* high for 3MCLK, low for 4) 1: Standard (RAS* high for 2.5MCLK, low for 3.5) 5 CRT Write Buffer Depth Control If set there are 4 16bit levels, if clear one 16bit level. 7 CRT Refresh disabled if set (LCD mode) 3C4h index 10h (R/W): HW Cursor X-position bit 0-7 When this value is written to the register, the upper 3 bits of the index register are taken as the low order bits of an 11 bit register. This is the horizontal position of the hardware cursor in pixels. 3C4h index 11h (R/W): HW Cursor Y-position7 bit 0-7 When this value is written to the register, the upper 3 bits of the index register are taken as the low order bits of an 11 bit register. This is the vertical position of the hardware cursor in pixels. 3C4h index 12h (R/W): HW Cursor control bit 0 Enable the hardware cursor if set 1 Enable Access to RAMDAC Extended Colors. Set to load special color values via 3C8h and 3C9h. When this bit is set palette entry 0 accesses the cursor background color and entry FFh accesses the cursor foreground color. 3C4h index 13h (R/W): HW Cursor bitmap address bit 0-1 Select 1 of 4 32x32 cursors The offset in 256 byte units within the last 16KB of video memory where the cursor mask and shape bitmaps are stored. There are two 128 byte (32x32 bits) bitmaps stored in video memory. The appearance of the cursor at each pixel is determined by a combination of the corresponding pixels from the first and second bitmap: 1st: 2nd: 0 0 The original screen pixel is shown (invisible cursor) 0 1 The pixel is shown in the cursor background color. 1 0 The pixel is shown as the inverse of the original screen pixel (XOR cursor) 1 1 The pixel is shown in the cursor foreground color. 3C4h index 14h (R/W): Scratch-Pad 2 bit 0-7 Reserved 3C4h index 15h (R/W): Scratch-Pad 3 bit 0-7 Reserved 3C4h index 16h (R/W): Miscellaneous bit 0-7 Reserved 3C4h index 19h (R/W): Scratch-Pad 4 bit 0-7 Reserved 3C4h index 1Ah (R/W): Miscellaneous bit 4 Enable 64x64 H/W cursor 5 Enable Improved cycle latency 6 Select dual-scan color panel 7 Select one DRAM refresh per line 3C4h index 1Bh (R/W): VCLK 0 Denominator & Post bit 0 VCLK 0 Post Scalar bit. Divide clock by 2 if set 1-5 VCLK 0 Denominator Data Note: The clock is (14.31818MHz * numerator (index 0Bh))/Denominator. Divide by 2 if the Post Scalar bit is set. 3C2h bits 2-3 selects between VCLK0, 1, 2 and 3 The 5420 can not handle frequencies above 75.2 MHz 3C4h index 1Ch (R/W): VCLK 1 Denominator & Post bit 0 VCLK 1 Post Scalar bit. Divide clock by 2 if set 1-5 VCLK 1 Denominator Data Note: See index 1Bh for the frequency calculation 3C4h index 1Dh (R/W): VCLK 2 Denominator & Post bit 0 VCLK 2 Post Scalar bit. Divide clock by 2 if set 1-5 VCLK 2 Denominator Data Note: See index 1Bh for the frequency calculation 3C4h index 1Eh (R/W): VCLK 3 Denominator & Post bit 0 VCLK 3 Post Scalar bit. Divide clock by 2 if set 1-5 VCLK 3 Denominator Data Note: See index 1Bh for the frequency calculation 3C4h index 1Fh (R/W): BIOS Write Enable and MCLK select bit 0-5 MCLK frequency bit 0-5 3CEh index 0 (R/W): Set/Reset bit 0-3 Write Mode 5 background color bits 0-3 4-7 Write Mode 5 background color bits 4-7 Note: See the VGA section for the use of this register in write mode 0-3 3CEh index 1 (R/W): Enable Set/Reset bit 0-3 Write Mode 4/5 foreground color bits 0-3 4-7 Enable SR plane 0-3 or Write Mode 4/5 foreground color bits 0-3 Note: See the VGA section for the use of this register in write mode 0-3 3CEh index 5 (R/W): Mode bit 0-1 Write mode: See the VGA section for modes 0-3. 2 Write mode bit 2 if 3CEh index 0Bh bit 2 is set mode 4: Foreground write ? mode 5: Fore and background write 3 Enable Read Color Compare 4 Enable odd/even (3C4h index 4 bit 2). 5 Shift 2 bits per byte 6 256 Color Mode 3CEh index 09h (R/W): Offset Register 0 bit 0-6 4k Primary/Low bank number If 3CEh index 0Bh bit 0 is set references to A000h-A7FFh use this bank register. If clear references to A000h-AFFFh use this bank register. 3CEh index 0Ah (R/W): Offset Register 1 bit 0-6 4k High bank number If 3CEh index 0Bh bit 0 is set references to A800h-AFFFh use this bank register. 3CEh index 0Bh (R/W): Extension Control bit 0 If set references to A000h-A7FFh use 3CEh index 9 as bank register, and references to A800h-AFFFh use 3CEh index 0Ah as bank register. If clear all references to A000h-AFFFh use 3CEh index 9 as bank register. 1 Enable BY8 Addressing for 256 color modes 2 Enable Extended Write Modes if set (mode 4 and 5) 3d4h index 00h (R/W): Horizontal Total (CX00) bit 0-7 Horizontal Total (-5) Note: This register is used in 80 column and mode 13h (3C4h index 1 bit 3 clear or 3CEh index 5 bit 6 set) 3d4h index 01h (R/W): Horizontal Total (CX01) bit 0-7 Horizontal Total (-5) Note: This register is used in 50 column modes (3D4h index 1 bit 3 set or 3CEh index 5 bit 6 clear) 3d4h index 02h (R/W): LFS Signal Vertical Counter Value Compare (CX02) bit 0-7 Used if autocentering is not selected. Note: This register selected for 3C2h bits 2-3 = 3 ?? 3d4h index 03h (R/W): LFS Signal Vertical Counter Value Compare (CX03) bit 0-7 Used if autocentering is not selected. Note: This register selected for 3C2h bits 2-3 = 2 ?? 3d4h index 04h (R/W): LFS Signal Vertical Counter Value Compare (CX04) bit 0-7 Used if autocentering is not selected. Note: This register selected for 3C2h bits 2-3 = 1 ?? 3d4h index 05h (R/W): LFS Signal Vertical Counter Value Compare (CX05) bit 0-7 Used if autocentering is not selected. Note: This register selected for 3C2h bits 2-3 = 0 ?? 3d4h index 06h (R/W): LFS Overflow (CX06) bit 0-1 Bits 8-9 of the LFS compare for 3C2h bits 2-3 = 3 2-3 Bits 8-9 of the LFS compare for 3C2h bits 2-3 = 2 4-5 Bits 8-9 of the LFS compare for 3C2h bits 2-3 = 1 6-7 Bits 8-9 of the LFS compare for 3C2h bits 2-3 = 0 3d4h index 06h (R/W): Vertical Total (RX06) bit 0-7 Vertical Total (-2) 3d4h index 07h (R/W): Color TFT Panel Control Signal (CX07) bit 0 If set FPVDCLK is always active, if clear FPVDCLK is gated by display enable 1 FPVDCLK is inverted if set 2 If set use LLCLK as HSYNC 3 If set use LFS as VSYNC 3d4h index 07h (R/W): Vertical Overflow (RX07) bit 0 Vertical Total bit 8 1 Vertical Displayed bit 8 2 Vertical Sync Start bit 8 3 Vertical Blank Start bit 8 4 Line Compare bit 8 5 Vertical Total bit 9 6 Vertical Displayed bit 9 7 Vertical Sync Start bit 9 3d4h index 08h (R/W): STN Color Panel Data Format (CX08) bit 0 If set 8bit data, if clear 16bit 1 Set for Dual shift clk STN, clear for single 2 Set for testing purposes only 3 Set to Shorten LP width, clear to Lengthen LP width 4 Set to enable foreground text enhancement 5 Set for Single Scan Mono Panels, clear for Dual Scan 6 Set for testing purposes only 7 Set to boost contrast for Mono Panels 3d4h index 09h (R/W): TFT Panel Data Format (CX09) bit 0-1 Data format. 0: 9bit(333), 2: 12bit(444), 1,3: 18bit direct 2-4 Shiftclock delay from internal character clock to TFT hsync(LLCLK) signal 3d4h index 0Ah (R/W): TFT Panel HSYNC Position Control (CX0A) bit 0-7 Horizontal counter to generate TFT panel VSYNC signal. Set in multiples of 8 VCLKs (80 column character clocks) 3d4h index 0Bh (R/W): Panel Adjustment Control (CX0B) (6235 only) bit 0-4 Number of LLCLKs between upper and lower panel halfs 5-6 Offset adjustment for gray-scale shading 3d4h index 10h (R/W): Vertical Sync Start (RX10) bit 0-7 VSYNC Start 3d4h index 11h (R/W): Vertical Sync End (RX11) bit 0-3 VSYNC End. 4 Clear Vertical Sync Interrupt 5 Enable Vertical Sync Interrupt 6 Select 5 refresh cycles 7 Write protect index 0-7. 3d4h index 15h (R/W): Vertical Blank Start (RX15) bit 0-7 Vertical Blank Start 3d4h index 16h (R/W): Vertical Blank End bit 0-7 Vertical Blank End 3d4h index 19h (R/W): Interlace End bit 0-7 Ending Horizontal Character Count for Odd field VSYNC. Typically half the horizontal total 3d4h index 1Ah (R/W): Miscellaneous Control bit 0 Enable Interlace sync/video data in Graphics mode or interlace only in Text mode. Set if an interlaced mode. 1 Enable Double-Buffered Display Start Address 3d4h index 1Bh (R/W): Extended Display Control bit 0 Display Start Address bit 16. Bit 0-15 are in 3d4h index Ch-Dh. 1 Enable Extended Address Wrap. Set to enable access to video memory beyond 128K (16bit memory) or 256K (32bit memory) 5 Set RAMDAC blanking=display enable signal (no border) 6 Select Text mode Fast-Page (132 color text) 7 Disable Cursor blink in Text Mode 3d4h index 1Ch (R/W): Flat-Panel Interface bit 0 Invert LFS signal 1 Invert LLCLK signal 2 Enable MCLK power-down during suspend mode 3 Protect CRTC for LCD timing: 3d4h index 0,1,6,7(bits 0,2,5,7), 10h and 11h 5 Enable extra LLCLK. Used for adjusting 242 line dual panel 6-7 Flat-Panel type. 0: Dual Mono, 1: Plasma/EL, 2: STN color, 3: TFT color 3d4h index 1Dh (R/W): Flat Panel Display Control bit 0 Enable Auto Center 1 Enable Auto Expand: 3C2h bit 6-7: 1: 400/200 lines, 2: 350, 3: 480. 2 Enable VGA access to reset Backlight Timer 3 Enable input ACTi to reset Backlight Timer 4 Suspend mode Clock source. If set use OSC, if clear use pin 32KHz. 5 Enable VGA access to reset Standby Timer 6 Enable input ACTi to reset Standby Timer 7 Enable access to LCD timing register at CRTC alternate index if set 3d4h index 1Eh (R/W): Flat Panel Shading bit 0 Enable Planar Graphics Mode Dithering 1 Enable Text mode Contrast Enhancement 2-3 # of shades for Flat Pane: Mono: 0: 16, 1: 64, 2: 128, 3:256 Color: 0: 4K, 1-3: 256K 4 Reverse Video Graphics Modes 5 Reverse Video Text Modes 6-7 Shade Mapping. 0: 18bit LUT output to 64 shades with NTSC weighting 1: green LUT output (6 bit to 64 shades). 2: Display data before Attribute Controller to 64 shades 3: Attribute Controller output, 6bitrs to 64 shades 3d4h index 1Fh (R/W): Flat Panel MOD control bit 0-6 If bit 7 is set LLCLK = (this value) + 180h if clear this is the number of scan lines after which the MOD pin will change polarity. 7 Modulation select. Set for internal Modulation, clear for external 3d4h index 20h (R/W): Power Management bit 0 Text Mode Shading Control. If set the text shades are derived the same way as the graphics, if clear the text shades are derived directly from the FG/BG data. 1-2 Select Refresh Rate. 0: 8ms, 2: 64ms, 2: self refresh, 3: no refresh 3 Activate Suspend Mode (timer override) 4 Activate Standby Mode (timer override) 5 Enable LCD mode if set 6 Enable CRT mode if set 7 set pin STANDBY to 'activate' output 3d4h index 21h (R/W): Power Down Timer Control bit 0-3 Standby Mode Timer Control. 0: disable timer, 1-15: minutes 4-7 Backlight Timer Control (FPBack) 3d4h index 23h (R/W): Suspend Mode Input Switch Debounce Timer bit 0 FPVcc output state (if bit1 set) 1 FPVcc control override 2 FPBack output state (if bit3 set) 3 FPBack control override 4-7 Time for input SUSPEND to remain active before entering suspend mode. 0: disable timer checking, 1-15: seconds 3d4h index 25h (R/W): Part Status Register bit 0-7 Part Status. Used for factory testing only. 3d4h index 27h (R): Part ID register bit 0-1 Revision Level 3 Set to 1 ??? 6-7 Device Identifier. 0: CL-GD6205 (C9h rev -BL) 1: CL-GD6235 (89h rev -BK) 2: CL-GD6215 (48h) 3: CL-GD6225 (09h rev -BK) Note: One source claims the 5428 has ID 24h & Rev 1 I.e. code. 91h Note: I've seen one chip marked as 5422-80, which returns 94h i.e. a 5424. 3d4h index 29h (R/W): Configuration Read Back bit 0 Bus Type Select. 0: Local Bus, 1: ISA bus 1-2 Local Bus Type 3 DRAM Type Select. 0: Dual CAS DRAM, 1: Dual write enable DRAM 4 Active NPD (no power down) input 5 Power up/down cycling activity GD5402, 542x and 543x series: 3C4h index 2 (R/W): Map Mask bit 0-7 Enable writing pixel bits 0-7 ????? Note: See the VGA section for the normal use of this register 3C4h index 6 (R/W): Unlock ALL Extensions bit 0-2,4 Writing 12h to this register enables extensions. Read back 0Fh if locked. Bits 3,5-7 are ignored on write. 3C4h index 7 (R/W): Extended Sequencer Mode bit 0 Enable High-Resolution 256 Color modes if set 1-2 (542x,02) Select CRTC Character Clock Divider 1-3 (543x) Select CRTC Character Clock Divider. 0: Normal operation 1: Clock/2 for 16bit pixels 2: Clock/3 for 24bit pixels 3: (5426-3x only) 16bit pixel data at Pixel Rate 4: (543x only) 32bit pixel data at Pixel Rate 4-7 (5422-3x) Select 1M Video Memory Mapping. The address in 1MB units the Video Memory is mapped at (0=no mapping) 3C4h index 8 (R/W): EEPROM Control bit 0 "CS" out to EEPROM 1 Enable EEPROM data input 2 "SK" to EEPROM thru ESYNC (if bit 4 is set) 3 "DI" to EEPROM thru EVIDEO (if bit 4 is set) 4 Enable EEPROM Data and Sk. If set ESYNC/EVIDEO* are outputs, if clear inputs 5 Latch ESYNC/EVIDEO* 6 Disable MEMCS16* for display memory 7 (R) EEPROM Input Data 3C4h index 9 (R/W): Scratch Register 0 bit 2-4 Monitor type. 0: 31,5kHz Std VGA. IBM 8512,8503 1: 31.5, 35.5 kHz IBM 8514 2: 31.5, 35.1 kHz NEC 2A 3: 31.5 - 35.5 kHz NEC II 4: 31.5 - 38 kHz Multi Freq. NEC 3D 5: 31.5 - 48 kHz Sony CPD-1304, NEC 3FG, Nanao 9065S, 9070U 6: 31.5 - 56.5 kHz NEC 4D,4FG, Nanao T240i 7: 31.5 - 64 kHz NEC 5D,5FG/6FG, Nanao T560i,T660i 3C4h index 0Ah (R/W): Scratch Register 1 bit 0-1 (5402) Display Memory. 0: 256K, 1: 512K, 2: 1M 3-4 (54xx) Video memory. 0=256K, 1=512K, 2=1024K, 3=2048K Note: Video memory should be determined from this register rather than index 0Fh 3C4h index 0Bh (R/W): VCLK 0 Numerator Register bit 0-6 VCLK 0 Numerator bits 0-6 3C4h index 0Ch (R/W): VCLK 1 Numerator Register bit 0-6 VCLK 1 Numerator bits 0-6 3C4h index 0Dh (R/W): VCLK 2 Numerator Register bit 0-6 VCLK 2 Numerator bits 0-6 3C4h index 0Eh (R/W): VCLK 3 Numerator Register bit 0-6 VCLK 3 Numerator bits 0-6 3C4h index 0Fh (R/W): DRAM Control bit 0-1 (542x) MCLK Select: 0: 50.1 MHz, 1: 44.7 MHz, 2: 41.2 MHz, 3: 37.6 MHz 0 (543x) (R) Disable DAC 1 (543x) MCLK Timing. 0: 50.11363MHz, 1: 41.16477MHz 2 RAS* Timing. 0: Extended (PD on MD[27], RAS* high for 3MCLK, low for 4) 1: Standard (RAS* high for 2.5MCLK, low for 3.5) 3-4 (54xx) DRAM Data Width. (542x) 0: 8bit (256K), 1: 16bit (512K), 2: 32bit (1M/2M) (543x) 2: 32bit, 3:64 bit 5 (5422-3x) CRT FIFO Depth Control 6 (542x) Disable CRTC FIFO Fast-Page detection Mode (543x) CPU Write Buffer Control 7 (5426-28) DRAM Bank Select. 0: 4 512Kx8, 1: 4 256Kx16 Set to enable access to memory beyond 1MB ?? (543x) DRAM Bank Switch Control 3C4h index 10h (R/W): HW Cursor X-position bit 0-7 When this value is written to the register, the upper 3 bits of the index register are taken as the low order bits of an 11 bit register. This is the horizontal position of the hardware cursor in pixels. 3C4h index 11h (R/W): HW Cursor Y-position7 bit 0-7 When this value is written to the register, the upper 3 bits of the index register are taken as the low order bits of an 11 bit register. This is the vertical position of the hardware cursor in pixels. 3C4h index 12h (R/W): HW Cursor control bit 0 Enable the hardware cursor if set 1 Enable Access to RAMDAC Extended Colors. Set to load special color values via 3C8h and 3C9h. When this bit is set palette entry 0 accesses the cursor background color and entry FFh accesses the cursor foreground color. 2 (5422-3x) If set select 64x64 cursor, if clear 32x32. 7 (5424-3x) Overscan Color Protect 3C4h index 13h (R/W): HW Cursor bitmap address bit 0-5 Select 1 of 64 32x32 cursors 2-5 (5422-3x) Select 1 of 16 64x64 cursors (if index 12h bit 2 is set) The offset in 256 byte units within the last 16KB of video memory where the cursor mask and shape bitmaps are stored. There are two 128 byte (32x32 bits) bitmaps stored in video memory. The appearance of the cursor at each pixel is determined by a combination of the corresponding pixels from the first and second bitmap: 1st: 2nd: 0 0 The original screen pixel is shown (invisible cursor) 0 1 The pixel is shown in the cursor background color. 1 0 The pixel is shown as the inverse of the original screen pixel (XOR cursor) 1 1 The pixel is shown in the cursor foreground color. 3C4h index 14h (R/W): Scratch-Pad Register 2 (5426-3x only) bit 0-7 3C4h index 15h (R/W): Scratch-Pad Register 3 (5426-3x only) bit 0-7 3C4h index 16h (R/W): Performance Tuning (5424-3x only) bit 0-3 FIFO Demand Threshold 4-5 (5424-28) RDY# delay for memory write bits 0-1. 0: 1, 1,2: 2, 3: 4 4 (543x) LRDY# Delay for Memory Cycles 5 (543x) Readback of CF6 6-7 (5424-28) RDY# delay for I/O bits 0-1. 0,1: 1 2,3: 2 (543x) LRDY# Delay for I/O Cycles 3C4h index 17h (R/W): Configuration Readback and Extended Control (543x only) bit 0 Shadow DAC Writes on Local Bus 1 Power Down Palette Memory 2 Enable Memory-Mapped I/O 3-5 (R) System Bus Select MD[50:48] ?? 7 Disable DRAM Refresh 3C4h index 18h (R/W): Signature Generator Control (5422-3x only) bit 0 Enable/Status Signal Generator 1 Reset Signature Generator. Set to reset to an initial, defined condition. Clear to allow the Signal Generator to run. 2-4 Select Pixel Bus. The bit to input to the Signal Generator. 0: bit 0 ... 7: bit 7 5 Enable Data Generator 6 Disable DCLK/Pixel Bus Drivers. ** For testing only ** 7 Disable MCLK Driver. ** For Testing only ** 3C4h index 19h W(R/W): Signature Generator Result (5422-3x only) bit 0-15 Signal Generator Result 3C4h index 1Bh (R/W): VCLK 0 Denominator & Post bit 0 VCLK 0 Post Scalar bit. Divide clock by 2 if set 1-5 VCLK 0 Denominator Data Note: The clock is (14.31818MHz * numerator (index 0Bh))/Denominator. Divide by 2 if the Post Scalar bit is set. 3C2h bits 2-3 selects between VCLK0, 1, 2 and 3 The 5420 can not handle frequencies above 75.2 MHz 3C4h index 1Ch (R/W): VCLK 1 Denominator & Post bit 0 VCLK 1 Post Scalar bit. Divide clock by 2 if set 1-5 VCLK 1 Denominator Data Note: See index 1Bh for the frequency calculation 3C4h index 1Dh (R/W): VCLK 2 Denominator & Post bit 0 VCLK 2 Post Scalar bit. Divide clock by 2 if set 1-5 VCLK 2 Denominator Data Note: See index 1Bh for the frequency calculation 3C4h index 1Eh (R/W): VCLK 3 Denominator & Post bit 0 VCLK 3 Post Scalar bit. Divide clock by 2 if set 1-5 VCLK 3 Denominator Data Note: See index 1Bh for the frequency calculation 3C4h index 1Fh (R/W): BIOS Write Enable and MCLK select (5424-3x only) bit 0-5 MCLK frequency bit 0-5 6 (543x) Use MCLK as VCLK if set. 7 Enable BIOS write 3CEh index 0 (R/W): Set/Reset bit 0-3 Write Mode 5 background color bits 0-3 4-7 Write Mode 5 background color bits 4-7 Note: See the VGA section for the use of this register in write mode 0-3 3CEh index 1 (R/W): Enable Set/Reset bit 0-3 Write Mode 4/5 foreground color bits 0-3 4-7 Enable SR plane 0-3 or Write Mode 4/5 foreground color bits 0-3 Note: See the VGA section for the use of this register in write mode 0-3 3CEh index 5 (R/W): Mode bit 0-1 (index 0Bh bit 2 clear) Write mode nits 0-1 0-2 (index 0Bh bit 2 set) Write mode bit 0-2 See the VGA section for modes 0-3. mode 4: Foreground write ? mode 5: Fore and background write 3 Enable Read Color Compare 4 Enable odd/even (3C4h index 4 bit 2). 5 Shift 2 bits per byte 6 256 Color Mode 3CEh index 09h (R/W): Offset Register 0 bit 0-7 4K Primary/Low bank number. If 3CEh index 0Bh bit 0 is set references to A000h-A7FFh use this bank register. If clear references to A000h-AFFFh use this bank register. (5426-3x) If index 0Bh bit 5 is set this register is in units of 16KB, rather than 4KB 3CEh index 0Ah (R/W): Offset Register 1 bit 0-7 4K High bank number. If 3CEh index 0Bh bit 0 is set references to A800h-AFFFh use this bank register. (5426-3x) If index 0Bh bit 5 is set this register is in units of 16KB, rather than 4KB 3CEh index 0Bh (R/W): Extension Control bit 0 If set references to A000h-A7FFh use 3CEh index 9 as bank register, and references to A800h-AFFFh use 3CEh index 0Ah as bank register. If clear all references to A000h-AFFFh use 3CEh index 9 as bank register. 1 Enable BY8 Addressing for 256 color modes 2 Enable Extended Write Modes if set (mode 4 and 5) 3 Enable 8byte memory read Data Latch 4 Enable Enhanced Writes for 16bit pixels (if bit 2 is set) 5 (5426-3x) Offset Granularity. If set the bank registers are in 16K rather than 4K steps. 3CEh index 0Ch (R/W): Color Key Compare (5424-3x only) bit 0-7 Color Key Compare bits 0-7 3CEh index 0Dh (R/W): Color Key Compare Mask (5424-3x only) bit 0-7 Color Key Compare Key Mask 0-7 3CEh index 0Eh (R/W): Miscellaneous Control (543x only) bit 0 DCLK Output Divide by 2 1 Static HSYNC 2 Static VSYNC 3CEh index 0Fh (R/W: Display Compression Control (543x only) bit 0 Enable Compression 1 Horizontal Compression 2-4 Vertical Compression 3CEh index 10h (R/W): 16bit Pixel Background Color High Byte (5422-3x only) bit 0-7 Extended BackGround color bits 8-15 in write mode 5. This data sent to planes 1/3, data from 3CEh index 0 sent to 2/4 3CEh index 11h (R/W): 16bit Pixel Foreground Color High Byte (5422-3x only) bit 0-7 Extended ForeGround color bits 8-15 in write mode 4/5. This data sent to planes 1/3, data from 3CEh index 1 sent to 2/4 3CEh index 12h (R/W): Background Color Byte 2 (543x only) bit 0-7 Extended BackGround color bits 16-23 in write mode 5. 3CEh index 13h (R/W): Foreground Color Byte 2 (543x only) bit 0-7 Extended ForeGround color bits 16-23 in write mode 4/5. 3CEh index 14h (R/W): Background Color Byte 3 (543x only) bit 0-7 Extended BackGround color bits 24-31 in write mode 5. 3CEh index 15h (R/W): Foreground Color Byte 3 (543x only) bit 0-7 Extended ForeGround color bits 24-31 in write mode 4/5. 3CEh index 20h W(R/W): BLT Width (5426-3x only) bit 0-10 (5426-28) Number of pixels across in the BLIT area. 0-12 (543x) do 3CEh index 22h W(R/W): BLT Height (5426-3x only) bit 0-9 (5426-28) Number of lines in the BLIT area. 0-10 (543x) do 3CEh index 24h W(R/W): BLT Destination Pitch (5426-3x only) bit 0-11 (5426-28) Number of bytes in a scanline at the destination. 0-12 (543x) do 3CEh index 26h W(R/W): BLT Source Pitch (5426-3x only) bit 0-11 (5426-28) Number of bytes in a scanline at the source. 0-12 (543x) do 3CEh index 28h 3(R/W): BLT Destination Start (5426-3x only) bit 0-20 (5426-28) Destination address of the BLIT. 0-21 (543x) do 3CEh index 2Ch 3(R/W): BLT Source Start (5426-3x only) bit 0-20 (5426-28) Source address of the BLIT. 0-21 (543x) do 3CEh index 2Fh (R/W): Write Mask Destination (543x only) bit 0-2 Write Mask 7 Disable X-Y Offset Indexing 3CEh index 30h (R/W): BLT Mode (5426-3x only) bit 0 BLT Direction. Set to decrement addresses during BitBLT operations, clear to increment. 1 BLT Destination. Set if system memory, clear if display memory. 2 BLT Source. Set if system memory, clear if display memory. 3 Enable Color Expand with Transparency Compare 4 (5426-28) Color Expand/Transparency Width 4-5 (543x) do 6 Enable 8x8 Pattern Copy 7 Enable Color Expand 3CEh index 31h (R/W): BLT Start/Status (5426-3x only) bit 0 (R) BLT Status. Set if busy 1 Set to start BLT operation, clear to suspend 2 BLT Reset 3 (R) BLT Progress Status 3CEh index 32h (R/W): BLT Raster Operation (ROP) (5426-3x only) bit 0-7 BLT 2-operand Raster Operation. 00h 0 05h And 06h Destination 09h Source And Not Destination 0Bh Not Destination 0Dh Copy from source 0Eh 1 50h Not Source And Destination 59h Xor 6Dh Or 90h Nor 95h XNor ADh Source Or Not Destination D0h Not Source D6h Not Source Or Destination DAh NAnd 3CEh index 33h (R/W): BLT Reserved (543x only) 3CEh index 34h W(R/W): BLT Trans Color (5426/28 only) bit 0-15 BLT Transparency Color 3CEh index 38h W(R/W): BLT Trans Mask (5426/28 only) bit 0-15 BLT Transparency Color Mask 3d4h index 19h (R/W): Interlace End bit 0-7 Ending Horizontal Character Count for Odd field VSYNC. Typically half the horizontal total 3d4h index 1Ah (R/W): Miscellaneous Control bit 0 Enable Interlace sync/video data in Graphics mode or interlace only in Text mode. Set if an interlaced mode. 1 Enable Double-Buffered Display Start Address 2-3 Overlay/DAC Mode Switching Control 0: Normal Operation 1: with EVIDEO* 2: with EVIDEO* and Color Key (5424-3x only) 3: with Color Key 4-5 Horizontal Blank End Overflow bits 6-7 6-7 Vertical Blank End Overflow bits 8-9 3d4h index 1Bh (R/W): Extended Display Control bit 0 Display Start Address bit 16. Bit 0-15 are in 3d4h index Ch-Dh. 1 Enable Extended Address Wrap. Set to enable access to video memory beyond 128K (16bit memory) or 256K (32bit memory) 2 (5420-3x) Display Start Address bit 17 3 (5426-3x) Display Start Address bit 18 4 Bit 8 of the CRTC Offset register (3d4h index 13h) ?. 5 Blanking Control 6 Select Text mode Fast-Page (132 color text) 7 (5426-3x) Enable Blank End Extensions 3d4h index 1Ch (R/W): Sync Adjust and Genlock (543x only) bit 0-2 Horizontal Sync Start Adjust 3-5 Horizontal Total Adjust 6 Enable HSYNC GENLOCK 7 Enable VSYNC GENLOCK 3d4h index 1Dh (R/W): Overlay Extended Control (543x only) bit 0 Enable Alpha Overlay 1-2 DAC Mode Switching 3 Overlay Video Clocking Mode 4-5 Color Key Compare type 7 Extended Display Start Address bit 19. 3d4h index 25h (R/W): Part Status Register (not 5402) bit 0-7 Part Status 3d4h index 27h (R): Part ID register bit 0-1 Revision Level 2-7 (54xx) Device Identifier: 06h: Acumos AVGA2 ?? 22h: Depends on revision Level: CL-GD5402 Rev=0 (88h) CL-GD5402 rev 1 Rev=1 (89h) CL-GD5420 Rev=2 (8Ah) CL-GD5420 rev 1 Rev=3 (8Bh) 23h: CL-GD5422 (8Ch-8Fh) 24h: CL-GD5426 (90h-93h) 25h: CL-GD5424 (94h-97h) 26h: CL-GD5426 (98h-9Bh) 29h: CL-GD543x (A4h-A7h) Note: One source claims the 5428 has ID 24h & Rev 1 I.e. code. 91h Note: I've seen one chip marked as 5422-80, which returns 94h i.e. a 5424. Memory locations: $C000:$8 1 byte Offset of Model string in BIOS. ID Cirrus VGA: (* First test for Cirrus 54xx *) old:=rdinx($3C4,6); wrinx($3C4,6,0); if rdinx($3C4,6)=$F then begin wrinx($3c4,6,$12); if (rdinx($3C4,6)=$12) and testinx2($3C4,$1E,$3F) then begin SubVers:=rdinx($3d4,$27); if testinx($3CE,9) then case SubVers of $88:name:='Cirrus CL-GD5402'; $89:name:='Cirrus CL-GD5402 r1'; $8A:name:='Cirrus CL-GD5420'; $8B:name:='Cirrus CL-GD5420 r1'; $8C..$8F:name:='Cirrus CL-GD5422'; $90..$93:name:='Cirrus CL-GD5426'; $94..$97:name:='Cirrus CL-GD5424'; $98..$9B:name:='Cirrus CL-GD5428'; $A4..$A7:name:='Cirrus CL-GD543x'; else UNK('Cirrus54',x); end else if testinx($3C4,$19) then case SubVers shr 6 of 0:name:='Cirrus CL-GD6205'; 1:name:='Cirrus CL-GD6235'; 2:name:='Cirrus CL-GD6215'; 3:name:='Cirrus CL-GD6225'; end else name:='Cirrus AVGA2 (5402)'; end; end else wrinx($3C4,6,old); (* Now test for 64xx *) old:=rdinx($3CE,$A); wrinx($3CE,$A,$CE); if rdinx($3CE,$A)=0 then begin wrinx($3CE,$A,$EC); if rdinx($3CE,$A)=1 then begin SubVers:=rdinx($3CE,$AA); case SubVers shr 4 of 4:name:='Cirrus CL-GD6440'; 5:name:='Cirrus CL-GD6412'; 6:name:='Cirrus CL-GD5410'; 7:name:='Cirrus CL-GD6420'; 8:name:='Cirrus CL-GD6410'; else UNK('Cirrus64') end; end; end; wrinx($3CE,$A,old); (* Now test for 5/600 *) old6:=rdinx($3C4,6); old:=rdinx(base,$C); outp(base+1,0); SubVers:=rdinx($3d4,$1F); wrinx($3C4,6,(eagle shl 4)+(eagle shr 4)); if inp($3C5)=0 then begin outp($3C5,SubVers); if inp($3C5)=1 then case SubVers of $EC:Cirrus 510/520; $CA:Cirrus 610/620; $EA:Cirrus Video7 OEM; else UNK(Cirrus) end; end; wrinx(base,$C,old); wrinx($3C4,6,old6); Modes for the GD 5320: 18h T 132 25 2 19h T 132 34 2 1Ah T 132 44 2 1Ch T 132 25 16 1Dh T 132 43 16 1Eh T 132 44 16 23h T 132 25 16 24h T 132 28 16 25h G 640 480 16 PL4 29h G 800 600 16 PL4 2Dh G 640 350 256 P8 60h T 132 25 61h G 640 400 16 PL4 61h T 132 50 HUH ?? 62h G 640 450 16 PL4 70h G 360 480 256 P8 71h G 528 400 256 P8 72h G 528 480 256 P8 74h G 320 240 256 P8 75h G 640 400 256 P8 Modes for the GD 54xx: 14h T 132 25 16 (8x16) 54h T 132 43 16 (8x8) 55h T 132 25 16 (8x14) 56h T 132 43 2 (5402 only) 57h T 132 25 2 (5402 only) 58h G 800 600 16 PL4 59h G 800 600 2 (5402 only) 5Ch G 800 600 256 P8 5Dh G 1024 768 16 PL4 5Eh G 640 400 256 P8 (5402 only) 5Fh G 640 480 256 P8 60h G 1024 768 256 P8 64h G 640 480 64K P16 65h G 800 600 64K P16 66h G 640 480 32K P15 67h G 800 600 32K P15 6Ah G 800 600 16 PL4 6Ch G 1280 1024 16 PL4 6Dh G 1280 1024 256 P8 6Fh G 320 200 64K P16 70h G 320 200 16M P24 71h G 640 480 16M P24 74h G 1024 768 64K P16 -- BIOS extensions -- ----------1012-80---------------------------------- INT 10 - VIDEO Cirrus Logic - Get Chip ID AH = 12h BL = 80h Return: AL = Chip ID: 2 CL-GD 510/610 3 CL-GD 610/620 4 CL-GD 5320 5 CL-GD 6410 6 CL-GD 5410 7 CL-GD 6420 8 CL-GD 6412 9 CL-GD 6416 10h CL-GD 5401 11h CL-GD 5402 12h CL-GD 5420 13h CL-GD 5422 14h CL-GD 5424 15h CL-GD 5426 16h CL-GD 5420 rev 1 ?? 17h CL-GD 5402 rev 1 ?? 18h CL-GD 5428 20h CL-GD 6205 21h CL-GD 6215 22h CL-GD 6225 30h CL-GD 5432 31h CL-GD 5434 40h CL-GD 6440 41h CL-GD 6450 BL = Silicon Revision number (bit 7 set if not available) BH = bit 2 set if using CL-GD 6340 LCD interface ----------1012-81--------------------------------------- INT 10 - VIDEO - Cirrus Logic - Get BIOS Version AH = 12h BL = 81h Return: AH = Major Version AL = Minor Version ----------1012-82--------------------------------------- INT 10 - VIDEO - Cirrus Logic - GET DESIGN REVISION CODE AH = 12h BL = 82h Return: AL = Chip Revision AH = ?? ----------1012-85--------------------------------------- INT 10 - VIDEO - Cirrus Logic - Get Memory AH = 12h BL = 85h Return: AL = Video Memory in 64K units --------V-1012--BL89------------------------- INT 10 - Cirrus Logic BIOS v3.02 - LCD panel - EN/DISABLE REVERSE VIDEO MODE AH = 12h BL = 89h AL = new state (00h enabled, 01h disabled) --------V-1012--BL8A------------------------- INT 10 - Cirrus Logic BIOS v3.02 - LCD panel - SET FRAME COLOR AH = 12h BL = 8Ah AL = new grey-scale color (00h = black to 0Fh = white) --------V-1012--BL8B------------------------- INT 10 - Cirrus Logic BIOS v3.02 - LCD panel - ENABLE/DISABLE BOLD MODE AH = 12h BL = 8Bh AL = new state (00h enabled, 01h disabled) --------V-1012--BL8C------------------------- INT 10 - Cirrus Logic BIOS v3.02 - LCD panel - SET AUTOMAP/EMULATE ATTRIBUTES AH = 12h BL = 8Ch AL = new state 00h enable automap 01h disable automap and emulate attributes --------V-1012--BL8F------------------------- INT 10 - Cirrus Logic BIOS v3.02 - LCD panel - ENABLE/DISABLE EXPAND MODE AH = 12h BL = 8Fh AL = new state (00h enabled, 01h disabled) Note: when expand mode is enabled, the vertical dimension is enlarged to full screen --------V-1012--BL90------------------------- INT 10 - Cirrus Logic BIOS v3.02 - LCD panel - SET CENTERING MODE AH = 12h BL = 90h AL = new position 00h centered 01h from top 02h from bottom 03h from top --------V-1012--BL91------------------------- INT 10 - Cirrus Logic BIOS v3.02 - LCD panel - SET 720-DOT FIXUP MODE AH = 12h BL = 91h AL = new mode 00h display MGA mode from left of screen (default) 01h display MGA from right 02h skip every ninth pixel 03h OR every 8th and 9th pixel --------V-1012--BL92------------------------- INT 10 - Cirrus Logic BIOS v3.02 - LCD panel - SWITCH DISPLAY AH = 12h BL = 92h AL = new display (00h LCD, 01h external monitor) Note: the deselected display is disabled ----------1012-93--------------------------------------- INT 10 - VIDEO - Cirrus Logic - FORCE 8bit OR 16bit OPERATION AH = 12h BL = 93h AL = New I/O width (00h = 16bits, 01h = 8bits). --------V-1012--BL94------------------------- INT 10 - Cirrus Logic BIOS v3.02 - POWER CONSERVATION AH = 12h BL = 94h AL = new state (00h wake up monitor, 01h shut down display) Note: AL=01h is reported not to work properly on the LCD panel ----------1012-9A--------------------------------------- INT 10 - VIDEO - Cirrus Logic - GET USER OPTIONS AH = 12h BL = 9Ah Return: AX = Options Word 1: Bit 2-4 Monitor type 5-6 Maximum Vertical Resolution 10 Force 8bit operation 14 Vertical Refresh Frequency at 640x480 CX = Options Word 2: Bit 4-5 Vertical Refresh Frequency at 1280x1024 11-12 Vertical Refresh Frequency at 800x600 13-15 Vertical Refresh Frequency at 1024x768 ----------1012-A0--------------------------------------- INT 10 - VIDEO - Cirrus Logic - GET VIDEO MODE AVAILABILITY AH = 12h AL = Video mode number BL = A0h Return: AH = Bit 0: Video mode supported BX = Offset of BIOS subrutine to fixup standard video parameters. (Call subrutine with DS:SI and ES:DI as returned by this call) DS:SI -> Standard Video Parameters or FFFFh:FFFFh ES:DI -> Supplemental Video Parameters or FFFFh:FFFFh ----------1012-A1--------------------------------------- INT 10 - VIDEO - Cirrus Logic - READ MONITOR TYPE AND ID FROM 15PIN CONNECTOR AH = 12h BL = A1h Return: BH = Monitor ID: 00h-08h Reserved 09h IBM 8604/8507 0Ah IBM 8514 0Bh IBM 8515 0Dh IBM 8503 0Eh IBM 8512/8513 0Fh no monitor BL = Monitor Type. 00h: Color, 01h: Grayscale, 02h: Display ----------1012-A2--------------------------------------- INT 10 - VIDEO - Cirrus Logic - SET MONITOR HORIZONTAL RETRACE FREQUENCY AH = 12h BL = A2h AL = Monitor Type 00h Standard VGA 01h 8514-compatible (31.5 + 35.5 kHz) 02h SuperVGA (31.5 - 35.1 kHz) 03h Extended SuperVGA (31.5 - 35.5 kHz) 04h multi-frequency (31.5 - 37.8 kHz) 05h extended multi-frequency (31.5 - 48-0 kHz) 06h super multi-frequency (31.5 - 56.0 kHz) 07h extended super multi-frequency (31.5 - 64.0 kHz) ----------1012-A3--------------------------------------- INT 10 - VIDEO - Cirrus Logic - SET VGA REFRESH AH = 12h BL = A3h AL = refresh rate for 640x480 (00h normal, 01h high) ----------1012-A4--------------------------------------- INT 10 - VIDEO - Cirrus Logic - SET MONITOR TYPE AH = 12h BL = A4h AL = Bits 0-3 Maximum Vertical Resolution 0: 480, 1: 600, 2: 768, 3: 1024 4-7 Vertical Refresh at 640x480: 0: 60Hz, 1: 72Hz BH = Bits 0-3 Vertical Refresh at 800x600: 0: 56Hz, 1: 60Hz, 2: 72Hz 4-7 Vertical Refresh at 1024x768: 0: 87Hz i-laced, 1: 60Hz, 2: 70Hz, 3: 72Hz, 4: 76Hz CH = Bits 4-7 Vertical Refresh at 1280x1024: 0: 87Hz i-laced, 1: 60Hz, 2: 70Hz Many other functions exist in the range BL = 80h - A3h